ITM_Type 構造体

#include <core_cm3.h>

フィールド
union {
__O uint8_t   u8
__O uint16_t   u16
__O uint32_t   u32
}	PORT [32]
uint32_t	RESERVED0 [864]
__IO uint32_t	TER
uint32_t	RESERVED1 [15]
__IO uint32_t	TPR
uint32_t	RESERVED2 [15]
__IO uint32_t	TCR
uint32_t	RESERVED3 [29]
__IO uint32_t	IWR
__IO uint32_t	IRR
__IO uint32_t	IMCR
uint32_t	RESERVED4 [43]
__IO uint32_t	LAR
__IO uint32_t	LSR
uint32_t	RESERVED5 [6]
__I uint32_t	PID4
__I uint32_t	PID5
__I uint32_t	PID6
__I uint32_t	PID7
__I uint32_t	PID0
__I uint32_t	PID1
__I uint32_t	PID2
__I uint32_t	PID3
__I uint32_t	CID0
__I uint32_t	CID1
__I uint32_t	CID2
__I uint32_t	CID3

フィールド詳解

CID0

__I uint32_t CID0

Offset: ITM Component Identification Register #0

CID1

__I uint32_t CID1

Offset: ITM Component Identification Register #1

CID2

__I uint32_t CID2

Offset: ITM Component Identification Register #2

CID3

__I uint32_t CID3

Offset: ITM Component Identification Register #3

IMCR

__IO uint32_t IMCR

Offset: ITM Integration Mode Control Register

IRR

__IO uint32_t IRR

Offset: ITM Integration Read Register

IWR

__IO uint32_t IWR

Offset: ITM Integration Write Register

LAR

__IO uint32_t LAR

Offset: ITM Lock Access Register

LSR

__IO uint32_t LSR

Offset: ITM Lock Status Register

PID0

__I uint32_t PID0

Offset: ITM Peripheral Identification Register #0

PID1

__I uint32_t PID1

Offset: ITM Peripheral Identification Register #1

PID2

__I uint32_t PID2

Offset: ITM Peripheral Identification Register #2

PID3

__I uint32_t PID3

Offset: ITM Peripheral Identification Register #3

PID4

__I uint32_t PID4

Offset: ITM Peripheral Identification Register #4

PID5

__I uint32_t PID5

Offset: ITM Peripheral Identification Register #5

PID6

__I uint32_t PID6

Offset: ITM Peripheral Identification Register #6

PID7

__I uint32_t PID7

Offset: ITM Peripheral Identification Register #7

PORT

__O { ... } PORT[32]

Offset: 0x00 ITM Stimulus Port Registers

RESERVED0

uint32_t RESERVED0[864]

RESERVED1

uint32_t RESERVED1[15]

RESERVED2

uint32_t RESERVED2[15]

RESERVED3

uint32_t RESERVED3[29]

RESERVED4

uint32_t RESERVED4[43]

RESERVED5

uint32_t RESERVED5[6]

TCR

__IO uint32_t TCR

Offset: ITM Trace Control Register

TER

__IO uint32_t TER

Offset: ITM Trace Enable Register

TPR

__IO uint32_t TPR

Offset: ITM Trace Privilege Register

u16

__O uint16_t u16

Offset: ITM Stimulus Port 16-bit

u32

__O uint32_t u32

Offset: ITM Stimulus Port 32-bit

u8

__O uint8_t u8

Offset: ITM Stimulus Port 8-bit

---

この構造体詳解は次のファイルから抽出されました:

• inc/OTHER/core_cm3.h