RT-AICHIP-sample
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マクロ定義 | |
#define | LOOPBACK_MODE 0 /* 1 is loopback, 0 is normal operation. */ |
#define | SSP_SLAVE 0 /* 1 is SLAVE mode, 0 is master mode */ |
#define | TX_RX_ONLY |
#define | USE_CS 0 |
#define | SSP_DEBUG 0 |
#define | SSP_BUFSIZE 16 |
#define | FIFOSIZE 8 |
#define | DELAY_COUNT 10 |
#define | MAX_TIMEOUT 0xFF |
#define | SSP0_SEL (1 << 2) |
#define | SSPSR_TFE (1 << 0) |
#define | SSPSR_TNF (1 << 1) |
#define | SSPSR_RNE (1 << 2) |
#define | SSPSR_RFF (1 << 3) |
#define | SSPSR_BSY (1 << 4) |
#define | SSPCR0_DSS (1 << 0) |
#define | SSPCR0_FRF (1 << 4) |
#define | SSPCR0_SPO (1 << 6) |
#define | SSPCR0_SPH (1 << 7) |
#define | SSPCR0_SCR (1 << 8) |
#define | SSPCR1_LBM (1 << 0) |
#define | SSPCR1_SSE (1 << 1) |
#define | SSPCR1_MS (1 << 2) |
#define | SSPCR1_SOD (1 << 3) |
#define | SSPIMSC_RORIM (1 << 0) |
#define | SSPIMSC_RTIM (1 << 1) |
#define | SSPIMSC_RXIM (1 << 2) |
#define | SSPIMSC_TXIM (1 << 3) |
#define | SSPRIS_RORRIS (1 << 0) |
#define | SSPRIS_RTRIS (1 << 1) |
#define | SSPRIS_RXRIS (1 << 2) |
#define | SSPRIS_TXRIS (1 << 3) |
#define | SSPMIS_RORMIS (1 << 0) |
#define | SSPMIS_RTMIS (1 << 1) |
#define | SSPMIS_RXMIS (1 << 2) |
#define | SSPMIS_TXMIS (1 << 3) |
#define | SSPICR_RORIC (1 << 0) |
#define | SSPICR_RTIC (1 << 1) |
#define | WREN 0x06 /* MSB A8 is set to 0, simplifying test */ |
#define | WRDI 0x04 |
#define | RDSR 0x05 |
#define | WRSR 0x01 |
#define | READ 0x03 |
#define | WRITE 0x02 |
#define | RDSR_RDY 0x01 |
#define | RDSR_WEN 0x02 |
関数 | |
void | SSP_IRQHandler (void) |
void | SSPInit (void) |
void | SSPSend (uint8_t *Buf, uint32_t Length) |
void | SSPReceive (uint8_t *buf, uint32_t Length) |
#define TX_RX_ONLY |