22 LPC_IOCON->PIO2_0 = 0x0000;
23 LPC_GPIO2->DIR &= 0xfffe;
26 LPC_IOCON->PIO0_1 = 0x0000;
27 LPC_GPIO0->DIR &= 0xfffd;
30 LPC_IOCON->PIO1_8 = 0x0000;
31 LPC_GPIO1->DIR |= 0x0100;
34 LPC_IOCON->SWDIO_PIO1_3 = 0x00C1;
35 LPC_GPIO1->DIR |= 0x0008;
38 LPC_IOCON->PIO1_11 = 0x00C8;
39 LPC_GPIO1->DIR |= 0x0800;
42 LPC_IOCON->PIO0_7 = 0x0000;
43 LPC_GPIO0->DIR |=0x0080;
CMSIS Cortex-M3 Core Peripheral Access Layer Header File.