RT-USB-9AXIS-00
ssp.h
1 /*****************************************************************************
2  * ssp.h: Header file for NXP LPC134x Family Microprocessors
3  *
4  * Copyright(C) 2006, NXP Semiconductor
5  * All rights reserved.
6  *
7  * History
8  * 2006.07.19 ver 1.00 Preliminary version, first Release
9  *
10 ******************************************************************************/
11 #ifndef __SSP_H__
12 #define __SSP_H__
13 
14 /* There are there modes in SSP: loopback, master or slave. */
15 /* Here are the combination of all the tests.
16 (1) LOOPBACK test: LOOPBACK_MODE=1, TX_RX_ONLY=0, USE_CS=1;
17 (2) Serial EEPROM test: LOOPBACK_MODE=0, TX_RX_ONLY=0, USE_CS=0; (default)
18 (3) TX(Master) Only: LOOPBACK_MODE=0, SSP_SLAVE=0, TX_RX_ONLY=1, USE_CS=1;
19 (4) RX(Slave) Only: LOOPBACK_MODE=0, SSP_SLAVE=1, TX_RX_ONLY=0, USE_CS=1 */
20 
21 #define LOOPBACK_MODE 0 /* 1 is loopback, 0 is normal operation. */
22 #define SSP_SLAVE 0 /* 1 is SLAVE mode, 0 is master mode */
23 #define TX_RX_ONLY 0 /* 1 is TX or RX only depending on SSP_SLAVE
24  flag, 0 is either loopback mode or communicate
25  with a serial EEPROM. */
26 
27 /* if USE_CS is zero, set SSEL as GPIO that you have total control of the sequence */
28 /* When test serial SEEPROM(LOOPBACK_MODE=0, TX_RX_ONLY=0), set USE_CS to 0. */
29 /* When LOOPBACK_MODE=1 or TX_RX_ONLY=1, set USE_CS to 1. */
30 
31 #define USE_CS 0
32 #define SSP_DEBUG 0
33 
34 /* SPI read and write buffer size */
35 #define SSP_BUFSIZE 16
36 #define FIFOSIZE 8
37 
38 #define DELAY_COUNT 10
39 #define MAX_TIMEOUT 0xFF
40 
41 /* Port0.2 is the SSP select pin */
42 #define SSP0_SEL (1 << 2)
43 
44 /* SSP Status register */
45 #define SSPSR_TFE (1 << 0)
46 #define SSPSR_TNF (1 << 1)
47 #define SSPSR_RNE (1 << 2)
48 #define SSPSR_RFF (1 << 3)
49 #define SSPSR_BSY (1 << 4)
50 
51 /* SSP CR0 register */
52 #define SSPCR0_DSS (1 << 0)
53 #define SSPCR0_FRF (1 << 4)
54 #define SSPCR0_SPO (1 << 6)
55 #define SSPCR0_SPH (1 << 7)
56 #define SSPCR0_SCR (1 << 8)
57 
58 /* SSP CR1 register */
59 #define SSPCR1_LBM (1 << 0)
60 #define SSPCR1_SSE (1 << 1)
61 #define SSPCR1_MS (1 << 2)
62 #define SSPCR1_SOD (1 << 3)
63 
64 /* SSP Interrupt Mask Set/Clear register */
65 #define SSPIMSC_RORIM (1 << 0)
66 #define SSPIMSC_RTIM (1 << 1)
67 #define SSPIMSC_RXIM (1 << 2)
68 #define SSPIMSC_TXIM (1 << 3)
69 
70 /* SSP0 Interrupt Status register */
71 #define SSPRIS_RORRIS (1 << 0)
72 #define SSPRIS_RTRIS (1 << 1)
73 #define SSPRIS_RXRIS (1 << 2)
74 #define SSPRIS_TXRIS (1 << 3)
75 
76 /* SSP0 Masked Interrupt register */
77 #define SSPMIS_RORMIS (1 << 0)
78 #define SSPMIS_RTMIS (1 << 1)
79 #define SSPMIS_RXMIS (1 << 2)
80 #define SSPMIS_TXMIS (1 << 3)
81 
82 /* SSP0 Interrupt clear register */
83 #define SSPICR_RORIC (1 << 0)
84 #define SSPICR_RTIC (1 << 1)
85 
86 /* ATMEL SEEPROM command set */
87 #define WREN 0x06 /* MSB A8 is set to 0, simplifying test */
88 #define WRDI 0x04
89 #define RDSR 0x05
90 #define WRSR 0x01
91 #define READ 0x03
92 #define WRITE 0x02
93 
94 /* RDSR status bit definition */
95 #define RDSR_RDY 0x01
96 #define RDSR_WEN 0x02
97 
98 /* If RX_INTERRUPT is enabled, the SSP RX will be handled in the ISR
99 SSPReceive() will not be needed. */
100 extern void SSP_IRQHandler (void);
101 extern void SSPInit( void );
102 extern void SSPSend( uint8_t *Buf, uint32_t Length );
103 extern void SSPReceive( uint8_t *buf, uint32_t Length );
104 
105 #endif /* __SSP_H__ */
106 /*****************************************************************************
107 ** End Of File
108 ******************************************************************************/